// ******************************************************************************
// Copyright     :  Copyright (C) 2020, Hisilicon Technologies Co. Ltd.
// File name     :  lcam_reg_offset.h
// Project line  :
// Department    :
// Author        :  xxx
// Version       :  1.0
// Date          :
// Description   :  xxx
// Others        :  Generated automatically by nManager V5.1
// History       :  xxx 2020/05/14 16:55:24 Create file
// ******************************************************************************

#ifndef LCAM_REG_OFFSET_H
#define LCAM_REG_OFFSET_H

/* lcam_csr Base address of Module's Register */
#define CSR_LCAM_CSR_BASE (0x0)

/* **************************************************************************** */
/*                      lcam_csr Registers' Definitions                            */
/* **************************************************************************** */

#define CSR_LCAM_CSR_LCAM_VERSION_REG (CSR_LCAM_CSR_BASE + 0x0)          /* Version Log register */
#define CSR_LCAM_CSR_LCAM_INDRECT_CTRL_REG (CSR_LCAM_CSR_BASE + 0x4)     /* LCAM间接寻址控制寄存器 */
#define CSR_LCAM_CSR_LCAM_INDRECT_TIMEOUT_REG (CSR_LCAM_CSR_BASE + 0x8)  /* LCAM间接寻址TIMEOUT配置寄存器 */
#define CSR_LCAM_CSR_LCAM_INDRECT_DATA_0_REG (CSR_LCAM_CSR_BASE + 0xC)   /* LCAM间接寻址数据寄存器 */
#define CSR_LCAM_CSR_LCAM_INDRECT_DATA_1_REG (CSR_LCAM_CSR_BASE + 0x10)  /* LCAM间接寻址数据寄存器 */
#define CSR_LCAM_CSR_LCAM_INDRECT_DATA_2_REG (CSR_LCAM_CSR_BASE + 0x14)  /* LCAM间接寻址数据寄存器 */
#define CSR_LCAM_CSR_LCAM_SCAN_PERIOD_REG (CSR_LCAM_CSR_BASE + 0x18)     /* LCAM背景周期 */
#define CSR_LCAM_CSR_LCAM_SCAN_PERIOD_GRA_REG (CSR_LCAM_CSR_BASE + 0x1C) /* LCAM背景周期计数粒度 */
#define CSR_LCAM_CSR_LCAM_SCAN_EN_REG (CSR_LCAM_CSR_BASE + 0x20)         /* LCAM背景周期使能 */
#define CSR_LCAM_CSR_LCAM_COMMON_CFG_REG (CSR_LCAM_CSR_BASE + 0x24)      /* LCAM 其它的配置 */
#define CSR_LCAM_CSR_LCAM_UNCRT_ERR_REG \
    (CSR_LCAM_CSR_BASE + 0x28) /* LCAM 致命中断标记配置入口发生丢弃API错误时，中断信号都会输出到顶层 */
#define CSR_LCAM_CSR_LCAM_WRR_WEIGHT_REG (CSR_LCAM_CSR_BASE + 0x2C) /* LCAM TCAM 仲裁器权重 */
#define CSR_LCAM_CSR_LCAM_RING_RX_RQST_CORRECT_CNT_REG \
    (CSR_LCAM_CSR_BASE + 0x30) /* The number of correct api /flit received in RING interfaces */
#define CSR_LCAM_CSR_LCAM_RING_RX_RQST_ERR_CNT_REG \
    (CSR_LCAM_CSR_BASE + 0x34) /* The number of error api /flit received in RING interfaces */
#define CSR_LCAM_CSR_LCAM_RING_RX_RQST_DROP_CNT_REG \
    (CSR_LCAM_CSR_BASE + 0x38) /* The number of dropped api/flit  received in RING interfaces */
#define CSR_LCAM_CSR_LCAM_RING_TX_RQST_CORRECT_CNT_REG \
    (CSR_LCAM_CSR_BASE + 0x3C) /* The number of correct api/flit send to RING interfaces */
#define CSR_LCAM_CSR_LCAM_RING_TX_RQST_ERR_CNT_REG \
    (CSR_LCAM_CSR_BASE + 0x40) /* The number of error api/flit send to RING interfaces */
#define CSR_LCAM_CSR_LCAM_INT_VECTOR_REG (CSR_LCAM_CSR_BASE + 0x44)
#define CSR_LCAM_CSR_LCAM_INT_REG (CSR_LCAM_CSR_BASE + 0x48)          /* SMIR interrupt data */
#define CSR_LCAM_CSR_LCAM_INT_MASK_REG (CSR_LCAM_CSR_BASE + 0x4C)     /* SMIR interrupt mask configuration */
#define CSR_LCAM_CSR_LCAM_RING_ITF_ERR_REG (CSR_LCAM_CSR_BASE + 0x50) /* RING request channel 入口和出口发生的错误 */
#define CSR_LCAM_CSR_LCAM_RING_ITF_ERR_MASK_REG (CSR_LCAM_CSR_BASE + 0x54)
#define CSR_LCAM_CSR_LCAM_AD_ECC_ONE_BIT_ERR_REG (CSR_LCAM_CSR_BASE + 0x58)   /* LCAM AD memory发生ECC校验1比特错误 */
#define CSR_LCAM_CSR_LCAM_AD_ECC_TWO_BIT_ERR_REG (CSR_LCAM_CSR_BASE + 0x5C)   /* LCAM AD memory发生ECC校验2比特错误 */
#define CSR_LCAM_CSR_LCAM_TCAM_ECC_ONE_BIT_ERR_REG (CSR_LCAM_CSR_BASE + 0x60) /* LCAM TCAM IP发生ECC校验1比特错误 */
#define CSR_LCAM_CSR_LCAM_TCAM_ECC_TWO_BIT_ERR_REG (CSR_LCAM_CSR_BASE + 0x64) /* LCAM TCAM IP发生ECC校验2比特错误 */
#define CSR_LCAM_CSR_LCAM_CMD_ERR_REG (CSR_LCAM_CSR_BASE + 0x68)              /* 软件配置错误 */
#define CSR_LCAM_CSR_LCAM_CMD_ERR_MASK_REG (CSR_LCAM_CSR_BASE + 0x6C)
#define CSR_LCAM_CSR_LCAM_INIT_STATUS_REG (CSR_LCAM_CSR_BASE + 0x70)
#define CSR_LCAM_CSR_LCAM_ECC_ERR_INJ_REG (CSR_LCAM_CSR_BASE + 0x74) /* LCAM ECC memory error injection */
#define CSR_LCAM_CSR_LCAM_SRC_ERR_REG (CSR_LCAM_CSR_BASE + 0x80)
#define CSR_LCAM_CSR_LCAM_SRC_ERR_MASK_REG (CSR_LCAM_CSR_BASE + 0x84)
#define CSR_LCAM_CSR_LCAM_SRC_CFG_REG (CSR_LCAM_CSR_BASE + 0x88)
#define CSR_LCAM_CSR_LCAM_SRC_CFG_NODE_ID0_REG (CSR_LCAM_CSR_BASE + 0x8C)
#define CSR_LCAM_CSR_LCAM_SRC_CFG_NODE_ID1_REG (CSR_LCAM_CSR_BASE + 0x90)
#define CSR_LCAM_CSR_LCAM_MEM_CTRL_BUS_CFG0_REG (CSR_LCAM_CSR_BASE + 0x94)
#define CSR_LCAM_CSR_LCAM_MEM_CTRL_BUS_CFG1_REG (CSR_LCAM_CSR_BASE + 0x98)
#define CSR_LCAM_CSR_LCAM_MEM_CTRL_BUS_CFG2_REG (CSR_LCAM_CSR_BASE + 0x9C)
#define CSR_LCAM_CSR_LCAM_MEM_CTRL_BUS_CFG3_REG (CSR_LCAM_CSR_BASE + 0xA0)
#define CSR_LCAM_CSR_LCAM_MEM_CTRL_BUS_CFG4_REG (CSR_LCAM_CSR_BASE + 0xA4)
#define CSR_LCAM_CSR_LCAM_TCAM_CTRL_BUS_CFG_REG (CSR_LCAM_CSR_BASE + 0xA8)

#endif // LCAM_REG_OFFSET_H
